The present invention relates to a microcomputer and a control method thereof, and in particular a microcomputer and a control method thereof performing the transition of an operational mode.
A microcomputer, in general, has a plurality of operational modes. The operational modes include, for example, a RUN mode, a STANDBY mode and the like. The RUN mode is a mode of executing a usual processing. The STANDBY mode consumes lower current than the RUN mode. The RUN mode includes operational modes according to a plurality of different operation clocks for a CPU (Central Processing Unit). For example, the RUN mode includes a MAINRUN mode, a SUBRUN mode and the like. The MAINRUN mode makes the microcomputer to execute the maximum performance by using a high-speed clock. The SUBRUN mode makes the microcomputer to execute the minimum performance by using a low-speed clock. The STANDBY mode includes, for example, a STOP mode, a HALT mode and the like. The STOP mode minimizes current consumption by stopping the generation of the clock. The HALT mode suppresses current consumption by stopping the supply of the clock to the CPU, thereby enabling a high-speed return to the RUN mode.
For example, the microcomputer transits from the RUN mode to the HALT mode by a command of the CPU, when there is no operational request for the microcomputer for a predetermined period. Further, the microcomputer transits from the HALT mode to the RUN mode, by supplying the CPU with current by an interruption request or the like, when the microcomputer returns to enable to execute the usual processing. That is, the microcomputer returns from the STANDBY mode.
Japanese Unexamined Patent Application Publication No. 1-260517 discloses a technique relating to a microcomputer to transit an operational mode between a plurality of RUN modes having different clock sources. The microcomputer in accordance with Japanese Unexamined Patent Application Publication No. 1-260517 includes a selection switching means to switch to a certain clock source among the plurality of clock sources according to a cause of interrupt and to supply the selected clock source to the CPU, when an internal or external interrupt occurs. Further, the microcomputer saves the previous operational mode, when switching to the certain clock source, that is, transiting an operational mode, and transits to the saved operational mode, when returning from an interruption processing.
Now, an operational example of the microcomputer in accordance with Japanese Unexamined Patent Application Publication No. 1-260517 is explained. First, the microcomputer saves a clock source of a first RUN mode, when it transits from the first RUN mode to a second RUN mode by an interrupt routine. Further, the CPU executes the interrupt routine by a clock source of the second RUN mode. The CPU returns to the saved clock source of the first RUN mode by executing a return command at the end of the interrupt routine. Herewith, it enables to perform execution on the first RUN mode.